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?006 fairchild semiconductor corporation 1 www.fairchildsemi.com hcpl06xx rev. 1.0.6 hcpl06xx high speed-10 mbit/s logic gate optocouplers tm may 2006 hcpl0600, hcpl0601, hcpl0611, hcpl0630, hcpl0631, hcpl0661 high speed-10 mbit/s logic gate optocouplers single channel: hcpl0600, hcpl0601, hcpl0611 dual channel: hcpl0630, hcpl0631, hcpl0661 features compact so8 package ve ry high speed-10 mbit/s superior cmr f an-out of 8 over -40? to +85? logic gate output strobable output (single channel devices) wired or-open collector u .l. recognized (file # e90700) vde approval pending applications ground loop elimination lsttl to ttl, lsttl or 5-volt cmos line receiver, data transmission data multiplexing switching power supplies pulse transformer replacement computer-peripheral interface description the hcpl06xx optocouplers consist of an algaas led, opti- cally coupled to a very high speed integrated photo-detector logic gate with a strobable output (single channel devices). the devices are housed in a compact small-outline package. this output features an open collector, thereby permitting wired or outputs. the hcpl0600, hcpl0601 and hcpl0611 output consists of bipolar transistors on a bipolar process while the hcpl0630, hcpl0631, and hcpl0661 output consists of bipolar transistors on a cmos process for reduced power con- sumption. the coupled parameters are guaranteed over the temperature range of -40? to +85?. a maximum input signal of 5 ma will provide a minimum output sink current of 13 ma (fan out of 8). an internal noise shield provides superior com- mon mode rejection. pa ck ag e dimensions lead coplanarity : 0.004 (0.10) max 0.202 (5.13) pin 1 0.019 (0.48) 0.182 (4.63) 0.021 (0.53) 0.011 (0.28) 0.050 (1.27) typ 0.244 (6.19) 0.224 (5.69) 0.143 (3.63) 0.123 (3.13) 0.008 (0.20) 0.003 (0.08) 0.010 (0.25) 0.006 (0.16) sea ti ng plane 0.164 (4.16) 0.144 (3.66) note all dimensions are in inches (millimeters)
2 www.fairchildsemi.com hcpl06xx rev. 1.0.6 hcpl06xx high speed-10 mbit/s logic gate optocouplers truth table (positive logic) *dual channel devices or single channel devices with pin 7 not connected. a 0.1 ? bypass capacitor must be connected between pins 8 and 5. (see note 1) input enable output hhl lhh hlh llh h* nc* l* l* nc* h* single-channel circuit drawing (hcpl0600, hcpl0601 and hcpl0611) 1 2 3 4 5 6 7 8 n/c _ v cc v e v o gnd + n/c v f dual-channel circuit drawing (hcpl0630, hcpl0631 and hcpl0661) 1 2 3 4 5 6 7 8 + _ v f1 v cc v 01 v 02 gnd v f2 _ +
3 www.fairchildsemi.com hcpl06xx rev. 1.0.6 hcpl06xx high speed-10 mbit/s logic gate optocouplers absolute maximum ratings (no derating required up to 85?) recommended operating conditions *6.3 ma is a guard banded value which allows for at least 20% ctr degradation. initial input current threshold value is 5.0 ma or less symbol parameter value units t stg storage temperature -40 to +125 ? t opr operating temperature -40 to +85 ? emitter i f dc/average forward input current (each channel) single channel 50 ma dual channel v e enable input voltage not to exceed vcc by more than 500mv single channel 5.5 v v r reverse input voltage (each channel) 5.0 v p i po w er dissipation single channel 45 mw dual channel detector v cc (1 minute max) supply voltage 7.0 v i o output current (each channel) 50 ma v o output voltage (each channel) 7.0 v p o collector output power dissipation single channel 85 mw dual channel symbol parameter min max units i fl input current, low level 0 250 ? i fh input current, high level *6.3 15 ma v cc supply voltage, output 4.5 5.5 v v el enable voltage, low level 0 0.8 v v eh enable voltage, high level 2.0 v cc v t a operating temperature -40 +85 ? nf an out (ttl load) 8 ttl loads r l output pull-up 330 4k ?
4 www.fairchildsemi.com hcpl06xx rev. 1.0.6 hcpl06xx high speed-10 mbit/s logic gate optocouplers electrical characteristics (t a = -40? to +85? unless otherwise speci?d.) individual component characteristics switching characteristics (t a = -40? to +85?, v cc = 5 v, i f = 7.5 ma unless otherwise speci?d.) symbol parameter test conditions min typ** max unit v f emitter (i f = 10 ma) 1.8 v input forward voltage t a =25? 1.75 b vr input reverse breakdown voltage (i r = 10 ?) 5.0 v c in input capacitance (v f = 0, f = 1 mhz) pf ? vf/ ? ta input diode temperature coef?ient (i f = 10 ma) mv/? i cch detector (v e = 0.5 v) single channel 10 ma high level supply current (i f = 0 ma, v cc = 5.5 v) dual channel 15 i ccl low level supply current (v e = 0.5 v) single channel 13 ma (i f = 10 ma, v cc = 5.5v) dual channel 21 i el low level enable current (v cc = 5.5 v, v e = 0.5 v) single channel -1.6 ma i eh high level enable current (v cc = 5.5 v, v e = 2.0 v) single channel -1.6 ma v eh high level enable voltage (v cc = 5.5 v, i f = 10 ma) single channel 2.0 v v el low level enable voltage (v cc = 5.5 v, i f = 10 ma)(note 2) single channel 0.8 v symbol ac characteristics test conditions device min typ max unit t plh propagation delay time to output high level (note 3) (t a =25?) all 20 75 ns (r l = 350 ? , c l = 15 pf) (fig. 20) 100 t phl propagation delay time to output low level (note 4) (t a =25?) all 25 75 ns (r l = 350 ? , c l = 15 pf) (fig. 20) 100 |t phl -t plh | pulse width distortion (r l = 350 ? , c l = 15 pf) (fig. 20) all 35 ns t r output rise time (10-90%) (r l = 350 ? , c l = 15 pf)(note 5) (fig. 20) all 50 ns t f output fall time (90-10%) (r l = 350 ? , c l = 15 pf)(note 6) (fig. 20) all 12 ns t elh enable propagation delay time to output high level (i f = 7.5 ma, v eh = 3.5 v) (r l = 350 ? , c l = 15 pf) (note 7) (fig. 21) hcpl0600 hcpl0601 hcpl0611 20 ns t ehl enable propagation delay time to output low level (i f = 7.5 ma, v eh = 3.5 v) (r l = 350 ? , c l = 15 pf) (note 8) (fig. 21) hcpl0600 hcpl0601 hcpl0611 20 ns |cm h | common mode tr ansient immunity (at output high level) (r l = 350 ? ) (t a =25?) (i f = 0 ma, v oh (min.) = 2.0 v)(note 9)(fig. 22, 23) |v cm | = 10 v hcpl0600 hcpl0630 v/? |v cm | = 50 v hcpl0601 hcpl0631 5000 |v cm | = 1,000 v hcpl0611 10,000 hcpl0661 25,000 |cm h | common mode tr ansient immunity (at output low level) (r l = 350 ? ) (t a =25?) (i f = 7.5 ma, v ol (max.) = 0.8 v)(note 10)(fig. 22, 23) |v cm | = 10 v hcpl0600 hcpl0630 v/? |v cm | = 50 v hcpl0601 hcpl0631 5000 |v cm | = 1,000 v hcpl0611 10,000 hcpl0661 25,000
5 www.fairchildsemi.com hcpl06xx rev. 1.0.6 hcpl06xx high speed-10 mbit/s logic gate optocouplers t ransfer characteristics (t a = -40? to +85? unless otherwise speci?d.) isolation characteristics (t a = -40? to +85? unless otherwise speci?d.) ** all typical values are at v cc = 5 v, t a = 25? notes 1. the v cc supply to each optoisolator must be bypassed by a 0.1? capacitor or larger. this can be either a ceramic or solid tantalum capacitor with good high frequency characteristic and should be connected as close as possible to the package v cc and gnd pins of each device. 2. enable input - no pull up resistor required as the device has an internal pull up resistor. 3. t plh - propagation delay is measured from the 3.75 ma level on the high to low transition of the input current pulse to the 1.5v level on the low to high transition of the output voltage pulse. 4. t phl - propagation delay is measured from the 3.75 ma level on the low to high transition of the input current pulse to the 1.5v level on the high to low transition of the output voltage pulse. 5. t r - rise time is measured from the 90% to the 10% levels on the low to high transition of the output pulse. 6. t f - fall time is measured from the 10% to the 90% levels on the high to low transition of the output pulse. 7. t elh - enable input propagation delay is measured from the 1.5v level on the high to low transition of the input voltage pulse to the 1.5v level on the low to high transition of the output voltage pulse. 8. t ehl - enable input propagation delay is measured from the 1.5v level on the low to high transition of the input voltage pulse to the 1.5v level on the high to low transition of the output voltage pulse. 9. cm h - the maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in the high state (i.e., v out > 2.0 v). measured in volts per microsecond (v/?). 10. cm l - the maximum tolerable rate of fall of the common mode voltage to ensure the output will remain in the low output state (i.e. , v out < 0.8 v). measured in volts per microsecond (v/?). 11. device considered a two-terminal device: pins 1,2,3 and 4 shorted together, and pins 5,6,7 and 8 shorted together. symbol dc characteristics test conditions min typ** max unit i oh high level output current (v cc = 5.5 v, v o = 5.5 v) (i f = 250 ?, v e = 2.0 v) (note 2) 100 ? v ol low level output voltage (v cc = 5.5 v, i f = 5 ma) (v e = 2.0 v, i ol = 13 ma) (note 2) 0.6 v i ft input threshold current (v cc = 5.5 v, v o = 0.6 v, v e = 2.0 v, i ol = 13 ma) 5ma symbol characteristics test conditions min typ** max unit i i-o input-output insulation leakage current (relative humidity = 45%) (t a = 25?, t = 5 s) (v i-o = 3000 vdc) (note 11) 1.0* ? v iso withstand insulation test voltage (r h < 50%, t a = 25?) (i i-o 2 ?, t = 1 min.) (note 11) 3750 v rms r i-o resistance (input to output) (v i-o = 500 v) (note 11) 10 12 ? c i-o capacitance (input to output) (f = 1 mhz) (note 11) 0.6 pf
6 www.fairchildsemi.com hcpl06xx rev. 1.0.6 hcpl06xx high speed-10 mbit/s logic gate optocouplers t ypical performance curves (hcpl0600, hcpl0601 and hcpl0611 only) fig. 1 forward current vs. input forward voltage v f - forward voltage (v) i f - forward current (ma) fig. 2 output voltage vs. forward current i oh - high level output current ( a) i th - input threshold current (ma) fig. 3 input threshold current vs. temperature t a - temperature (?c) t a - temperature (?c) fig. 4 high level output current vs. temperature i f - forward input current (ma) v o - output voltage (v) 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 0.001 0.01 0.1 1 10 100 t a = 85 c t a = 70 c t a = 25 c t a = 0 c t a = -40 c 012345 0 1 2 3 4 5 6 t a = 25 c v cc = 5v r l = 350 ? r l = 1k ? -40 -20 0 20 4 06080100 0 1 2 3 4 5 v cc = 5v v o = 0.6v r l = 350 ? r l = 1k ? -40 -20 0 20 4 06080100 0 2 4 6 8 10 12 14 16 v o = v cc = 5.5v v e = 2v i f = 250 a
7 www.fairchildsemi.com hcpl06xx rev. 1.0.6 hcpl06xx high speed-10 mbit/s logic gate optocouplers t ypical performance curves (hcpl0600, and hcpl0601 and hcpl0611 only) fig. 5 low level output voltage vs. temperature t a - temperature (?c) t a - temperature (?c) t a - temperature (?c) v ol - low level output voltage (v) t p - propagation delay (ns) fig. 6 low level output current vs. temperature i ol - low level output current (ma) t p - propagation delay (ns) fig. 7 propagation delay vs. temperature fig. 8 propagation delay vs. pulse input current i f - pulse input current (ma) -40 -20 0 20 4 06080100 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 v cc = 5.5v v e = 2v i f = 5ma i o = 12.8ma i o = 9.6ma i o = 6.4ma i o = 16ma -40 -20 0 20 40 60 80 100 20 25 30 35 40 45 50 55 60 v cc = 5v v e = 2v v ol = 0.6v i f = 10-15ma i f = 5ma -40 -20 0 20 4 06080100 20 30 40 50 60 70 80 90 100 v cc = 5v i f = 7.5ma t plh r l = 1k ? t plh r l = 350 ? t phl rl = 350 ? & 1k ? 57911 13 15 20 30 40 50 60 70 80 90 v cc = 5v t a = 25 c t plh r l = 1k ? t plh r l = 350 ? t phl rl = 350 ? & 1k ?
8 www.fairchildsemi.com hcpl06xx rev. 1.0.6 hcpl06xx high speed-10 mbit/s logic gate optocouplers t ypical performance curves (hcpl0600, hcpl0601 and hcpl0611 only) fig. 9 typical enable propagation delay vs. temparature t a - temperature (?c) t a - temperature (?c) t a - temperature (?c) t e - enable propagation delay (ns) fig. 10 typical rise and fall time vs. temperature t f - f all time (ns) fig. 11 typical pulse width distortion vs. temperature pwd - pulse width distortion (ns) -40 -20 0 20 4 06080100 0 10 20 30 40 50 60 70 80 90 v cc = 5v v eh = 3v v el = 0v i f = 7.5ma t elh r l = 1k ? t elh r l = 350 ? t ehl rl = 350 ? & 1k ? -40 -20 0 20 4 06080100 0 40 80 120 160 200 240 v cc = 5v i f = 7.5ma t r r l = 1k ? t r r l = 350 ? t f r l = 350 ? & 1k ? -40 -20 0 20 4 06080100 0 5 10 15 20 25 30 35 40 v cc = 5v i f = 7.5ma r l = 1k ? r l = 350 ?
9 www.fairchildsemi.com hcpl06xx rev. 1.0.6 hcpl06xx high speed-10 mbit/s logic gate optocouplers t ypical performance curves (hcpl0630, hcpl0631 and hcpl0661 only) fig. 12 input forward current vs. forward voltage fig. 13 input threshold current vs. ambient temperature fig. 14 high level output current vs. ambient temperature fig. 15 low level output current vs. ambient temperature fig. 16 low level output voltage vs. ambient temperature v f - forward voltage (v) 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 i f - forward current (ma) t a = 85 c t a = 100 c t a = 25 c t a = 0 c t a = -40 c 0.8 0.001 0.01 0.1 1 10 100 i th - input threshold current (ma) t a - ambient temperature ( c) t a - ambient temperature ( c) t a - ambient temperature ( c) t a - ambient temperature ( c) -40 -20 0 20 40 60 80 100 0.0 0.5 1.0 1.5 2.0 2.5 v cc = 5.5v v o = 0.6v r l = 1k ? r l = 350 ? r l = 4k ? -40 -20 0 20 40 60 80 100 i oh - high level output current (na) 0 4 8 12 16 20 v o = v cc = 5.5v v e = 2v (single channel only) i f = 250 a -40 -20 0 20 40 60 80 100 i ol - low level output current (ma) 10 15 20 25 30 35 40 v cc = 5.5v v e = 2v (single channel only) v ol = 0.6v i f = 5 - 15ma -40 -20 0 20 40 60 80 100 v ol - low level output voltage (v) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 v cc = 5.5v v e = 2v (single channel only) i f = 5ma i o = 6.4ma i o = 9.6ma i o = 12.8ma i o = 16ma fig. 17 pulse width distortion vs. ambient temperature -40 -20 0 20 40 60 80 100 pwd - pulse width distortion (ns) 0 10 20 30 40 50 60 70 v cc = 5v i f = 7.5ma rl = 1k ? rl = 350 ? rl = 4k ? t a - ambient temperature ( c)
10 www.fairchildsemi.com hcpl06xx rev. 1.0.6 hcpl06xx high speed-10 mbit/s logic gate optocouplers t ypical performance curves (hcpl0630, hcpl0631 and hcpl0661 only) fig. 18 propagation delay vs. ambient temperature fig. 19 rise and fall times vs. ambient temperature t a - ambient temperature ( c) t a - ambient temperature ( c) -40 -20 0 20 40 60 80 100 0 20 40 60 80 100 120 v cc = 5v i f = 7.5ma t phl rl = 350 ? , 1k ? , 4k ? t plh rl = 350 ? t plh rl = 1k ? t plh rl = 4k ? t p - propagation delay (ns) -40 -20 0 20 40 60 80 100 t r - rise time (ns) 0 50 100 150 200 250 300 350 t f - fall time (ns) 0 1 2 3 4 5 6 7 v cc = 5v i f = 7.5ma t f - rl = 350 ? , 1k ? , 4k ? t r - rl = 350 ? t r - rl = 1k ? t r - rl = 4k ?
11 www.fairchildsemi.com hcpl06xx rev. 1.0.6 hcpl06xx high speed-10 mbit/s logic gate optocouplers phl t f i = 7.5 ma 1.5 v 90% 10% 7.5 ma +5v 1.5 v 3.0 v 1.5 v 3 2 1 4 8 7 6 5 plh t i = 3.75 ma f out put o (v ) input (i ) f out put (v ) o f t r t o z = 50 ? pulse generator tr = 5ns (v ) e input monitor gnd v cc o (v ) out put l r l c (v ) output o input (v ) e ehl t elh bypass .1 f fig. 20 test circuit and waveforms for t plh , t phl, t r and t f . fig. 21 test circuit t ehl and t elh . t 1 2 3 4 1 2 3 4 8 7 6 5 gnd v cc 8 7 6 5 dual channel pulse gen. z o = 50 ? t f = t r = 5 ns pulse gen. t f = t r = 5 ns z o = 50 ? +5 v i f v cc r m r l .1 f bypass c l +5v 47 ? r l input monitoring node input monitor (i f ) output (v o ) output v o monitoring node 0.1 f bypass c l * gnd t est circuit for hcpl0600, hcpl0601 and hcpl0611 t est circuit for hcpl0630, hcpl0631 and hcpl0661
12 www.fairchildsemi.com hcpl06xx rev. 1.0.6 hcpl06xx high speed-10 mbit/s logic gate optocouplers +5v peak 3 2 1 4 8 7 6 5 gnd v cc o (v ) output 350 ? v cm ff v a b pulse gen i f cm v 0v o v 5v switching pos. (a), i = 0 f o v (max) cm 0.5 v o v switching pos. (b), i = 7.5 ma f h cm l v (min) o bypass 0.1 f fig. 22 test circuit common mode transient immunity t est circuit for hcpl0600, hcpl0601, and hcpl0611 (hcpl0600, hcpl0601 and hcpl0611)
13 www.fairchildsemi.com hcpl06xx rev. 1.0.6 hcpl06xx high speed-10 mbit/s logic gate optocouplers peak cm v 0v o v 3.3v switching pos. (a), i = 0 f o v (max) cm 0.5 v o v switching pos. (b), i = 7.5 ma f h cm l v (min) o fig. 23 t (hcpl0630, hcpl0631 and hcpl0661) est circuit common mode transient immunity 1 2 3 4 8 b a 7 6 5 dual channel +3.3v i f v cc v cm pulse generator z o = 50 ? +? r l v ff output v o monitoring node 0.1 f bypass gnd te st circuit for hcpl0630, hcpl0631 and hcpl0661
14 www.fairchildsemi.com hcpl06xx rev. 1.0.6 hcpl06xx high speed-10 mbit/s logic gate optocouplers 8-pin small outline 0.024 (0.61) 0.050 (1.27) 0.155 (3.94) 0.275 (6.99) 0.060 (1.52)
15 www.fairchildsemi.com hcpl06xx rev. 1.0.6 hcpl06xx high speed-10 mbit/s logic gate optocouplers ordering information marking information option order entry identi?er description no suf? hcpl0600 shipped in tubes (50 units per tube) v hcpl0600v vde0884 (pending approval) r1 hcpl0600r1 tape and reel (500 units per reel) r1v hcpl0600r1v vde0884 (pending approval), tape and reel (500 units per reel) r2 hcpl0600r2 tape and reel (2500 units per reel) r2v hcpl0600r2v vde0884 (pending approval), tape and reel (2500 units per reel) 1 2 6 4 3 5 de?nitions 1f airchild logo 2d e vice number 3 vde mark (note: only appears on parts ordered with vde option ? see order entry table) 4 one digit year code, e.g., ? 5t wo digit work week ranging from ?1 to ?3 6 assembly package code 600 s yy x v
16 www.fairchildsemi.com hcpl06xx rev. 1.0.6 hcpl06xx high speed-10 mbit/s logic gate optocouplers carrier tape speci?cations re?ow pro?le 4.0 0.10 1.5 min user direction of feed 2.0 0.05 1.75 0.10 5.5 0.05 12.0 0.3 8.0 0.10 0.30 max 8.3 0.10 3.50 0.20 0.1 max 6.40 0.20 5.20 0.20 1.5 0.1/-0 300 280 260 240 220 200 180 160 140 120 100 80 60 40 20 0 c time (s) 0 60 180 120 270 260 c >245 c = 42 sec time above 183 c = 90 sec 360 1.822 c/sec ramp up rate 33 sec
17 www.fairchildsemi.com hcpl06xx rev. 1.0.6 hcpl06xx high speed-10 mbit/s logic gate optocouplers rev. i19 trademarks t he following are registered and unregistered trademarks fairchild semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. disclaimer fairchild semiconductor reserves the right to make changes without further notice to any pr oducts herein to improve reliability, function or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. these sp ec if ic at io ns do not expand the terms of fairchild?s worldwide terms and conditions, sp ec if ic a lly the warranty therein, which covers these products. life support policy fairchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms acex activearray bottomless bu ild it now coolfet cross volt dome ecos park e 2 cmos en signa fact fast fastr fps frfet gl obaloptoisolator gto hisec i 2 c i-lo im plieddisconnect in tellimax isoplanar littlefet microc oupler mi crofet mi cropak microwire m sx msxpro ocx ocxpro optologic optoplanar pacman pop po wer247 poweredge powersaver powertrench qfet qs qt optoel ectronics quiet series rapidconfigure rapidconnect serdes scalarpump silent switcher smart start spm stealth superfet supersot-3 supersot-6 supersot-8 sync fet tcm ti nylogic tinyopto tr utranslation uhc unifet ultrafet vcx wire fact quiet series ac ross the board. around the world. t he power franchise pr ogrammable active droop datasheet identification product status definition ad vance information formative or in design th is datasheet contains the design specifications for product development. specifications may change in any manner without notice. pr eliminary first production this datasheet contains preliminary data, and supplementary data will be published at a later date. fa ir child semiconductor reserves the right to make changes at any time without notice in order to improve design. no identification needed full production this datasheet contains final specifications. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. ob solete not in production this datasheet contains specifications on a product t hat has been discontinued by fairchild semiconductor. t he datasheet is printed for reference information only.

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